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TYPICAL APPLICATIONS
5. Equating pole 2 to 5 times the Crossover Frequency to
5 ? F CROSS = F
P2 =
1
2 ? ? R F ---------------------
SW x
VOUT x
INV x
L x
R Sx
C Sx
C Xx
R Fx
R1 x
R2 x
C Ox
achieve a faster response and a proper phase margin
-----------------------------------------
C F C X
C F + C x
COMP x
C Fx
C X ?
C F
2 ? * R F C F F P 2 ? 1
Figure 12. Type III compensation network
1. Choose a value for R1 (R2only applies to Channel 1)
2. Consider a Crossover frequency of one tenth of the
switching frequency, set the Zero pole frequency to
Fcross/10
TRACKING CONFIGURATIONS
The 34716 allows default Ratiometric tracking on channel
2 by connecting VDDQ to the VREFIN pin. It has an internal
resistor divider that allows an output of VDDQ/2.
LAYOUT GUIDELINES
F CROSS ?
C F ?
F P 0
?
1 1
10 2 ? * R 1 C F
1
2 ? * R 1 F PO
The layout of any switching regulator requires careful
consideration. First, there are high di/dt signals present, and
the traces carrying these signals need to be kept as short and
as wide as possible to minimize the trace inductance, and
therefore reduce the voltage spikes they can create. To do
this, an understanding of the major current carrying loops is
important. See Figure 13 . These loops, and their associated
components, should be placed in such a way as to minimize
3. Knowing the LC frequency, the Frequency of Zero 1
and Zero 2 in the compensation network is equal to
F LC
the loop size to prevent coupling to other parts of the circuit.
Also, the current carrying power traces and their associated
return traces should run adjacent to one another, to minimize
the amount of noise coupling. If sensitive traces must cross
F LC ?
F Z 2 ?
F Z 1 ?
1
2 ? L X C OX
1
2 ? * R F C F
? F Z 1 ? F Z 2
1
2 ? * R 1 C S
the current carrying traces, they should be made
perpendicular to one another to reduce field interaction .
Second, small signal components which connect to
sensitive nodes need consideration. The critical small signal
components are the ones associated with the feedback
circuit. The high impedance input of the error amp is
especially sensitive to noise, and the feedback and
compensation components should be placed as far from the
This gives the result
switch node, and as close to the input of the error amplifier as
possible. Other critical small signal components include the
R F ?
1
2 ? * C F F Z 1
C S ?
1
2 ? * R 1 F Z 2
bypass capacitors for VIN, VREFIN, and VDDI. Locate the
bypass capacitors as close to the pin as possible.
The use of a multi-layer printed circuit board is
recommended. Dedicate one layer, usually the layer under
the top layer, as a ground plane. Make all critical component
4. Calculate R S by placing the first pole at the ESR zero
frequency
ground connections with vias to this layer. Make sure that the
power grounds, PGND1 and PGND2 are connected directly
to the ground plane and not routed through the thermal pad
or analog ground. Dedicate another layer as a power plane
F ESR ?
R S ?
F P 1 ?
1
2 ? * Co X * ESR
1
2 ? * R S C S
? F P 1
1
2 ? * F P 1 C S
and split this plane into local areas for common voltage nets.
The IC input supply (VIN) should be connected with a
dedicated trace to the input supply This will help prevent
noise on the buck regulator's power inputs (PVIN1 and
PVIN2) from injecting switching noise into the IC’s analog
circuitry.
34716
Analog Integrated Circuit Device Data ?
22
Freescale Semiconductor
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